ARM Cortex-M Assembly Instructions

NOTE:   Ra Rd Rm Rn Rt represent 32-bit registers

  value   any 32-bit value: signed, unsigned, or address
{S}     if S is present, instruction will set condition codes
#im12   any value from 0 to 4095
#im16   any value from 0 to 65535
{Rd,}   if Rd is present Rd is destination, otherwise Rn
#n      any value from 0 to 31
#off    any value from -255 to 4095
label   any address within the ROM of the microcontroller
op2     the value generated by <op2> 

Arithmetic Instructions

ADD{S} {Rd,} Rn, <op2>   

ADD{S} {Rd,} Rn, #im12 

SUB{S} {Rd,} Rn, <op2>           

SUB{S} {Rd,} Rn, #im12 

RSB{S} {Rd,} Rn, <op2>              

RSB{S} {Rd,} Rn, #im12 

CMP    Rn, <op2>       

CMN    Rn, <op2>      

MUL{S} {Rd,} Rn, Rm   

MLA    Rd, Rn, Rm, Ra  

MLS    Rd, Rn, Rm, Ra   

UDIV   {Rd,} Rn, Rm    

SDIV   {Rd,} Rn, Rm    

; Rd = Rn + op2  

; Rd = Rn + im12, im12 is 0 to 4095

; Rd = Rn – op2          

; Rd = Rn – im12, im12 is 0 to 4095

; Rd = op2 – Rn            

; Rd = im12 – Rn

; Rn – op2      sets the NZVC bits

; Rn – (-op2)   sets the NZVC bits

; Rd = Rn * Rm       signed or unsigned        

; Rd = Ra + Rn*Rm    signed or unsigned

; Rd = Ra – Rn*Rm    signed or unsigned          

; Rd = Rn/Rm         unsigned

; Rd = Rn/Rm         signed

Logical Instructions

AND{S} {Rd,} Rn, <op2>

ORR{S} {Rd,} Rn, <op2>

EOR{S} {Rd,} Rn, <op2>

BIC{S} {Rd,} Rn, <op2>

ORN{S} {Rd,} Rn, <op2>

LSR{S} Rd, Rm, Rs

LSR{S} Rd, Rm, #n

ASR{S} Rd, Rm, Rs

ASR{S} Rd, Rm, #n

LSL{S} Rd, Rm, Rs

LSL{S} Rd, Rm, #n

; Rd=Rn&op2    (op2 is 32 bits)  

; Rd=Rn|op2    (op2 is 32 bits)

; Rd=Rn^op2    (op2 is 32 bits)  

; Rd=Rn&(~op2) (op2 is 32 bits)

; Rd=Rn|(~op2) (op2 is 32 bits)

; logical shift right Rd=Rm>>Rs  (unsigned)

; logical shift right Rd=Rm>>n   (unsigned)

 ; arithmetic shift right Rd=Rm>>Rs (signed)

 ; arithmetic shift right Rd=Rm>>n  (signed)

 ; shift left Rd=Rm<<Rs (signed, unsigned)

; shift left Rd=Rm<<n  (signed, unsigned)

Branch Instructions

B    label

BEQ  label

BNE  label

BCS  label

BHS  label

BCC  label  

BLO  label

BMI  label

BPL  label

BVS  label

BVC  label

BHI  label

BLS  label

BGE  label

BLT  label

BGT  label

BLE  label

BX   Rm

BL   label

BLX  Rm     

; branch to label    Always

; branch if Z == 1   Equal

; branch if Z == 0   Not equal

; branch if C == 1   Higher or same, unsigned ≥

; branch if C == 1   Higher or same, unsigned ≥

; branch if C == 0   Lower, unsigned

; branch if C == 0   Lower, unsigned <

; branch if N == 1   Negative

; branch if N == 0   Positive or zero

; branch if V == 1   Overflow

; branch if V == 0   No overflow

; branch if C==1 and Z==0  Higher, unsigned >

; branch if C==0 or  Z==1  Lower or same, unsigned ≤

; branch if N == V   Greater than or equal, signed ≥

; branch if N != V   Less than, signed <

; branch if Z==0 and N==V  Greater than, signed >

; branch if Z==1 or N!=V  Less than or equal, signed ≤

; branch indirect to location specified by Rm

; branch to subroutine at label

; branch to subroutine indirect specified by Rm 

Memory Access Instructions

LDR    Rd, [Rn]

LDR    Rd, [Rn,#off]

LDR    Rd, =value

LDRH   Rd, [Rn]

LDRH   Rd, [Rn,#off]

LDRSH  Rd, [Rn]

LDRSH  Rd, [Rn,#off]

LDRB   Rd, [Rn]

LDRB   Rd, [Rn,#off]

LDRSB  Rd, [Rn]

LDRSB  Rd, [Rn,#off]

STR    Rt, [Rn]

STR    Rt, [Rn,#off]

STRH   Rt, [Rn]

STRH   Rt, [Rn,#off]

STRB   Rt, [Rn]

STRB   Rt, [Rn,#off]

PUSH   {Rt}

POP    {Rd}

ADR    Rd, label

MOV{S} Rd, <op2>

MOV    Rd, #im16

MVN{S} Rd, <op2>    

; load 32-bit number at [Rn] to Rd

; load 32-bit number at [Rn+off] to Rd

; set Rd equal to any 32-bit value (PC rel)

; load unsigned 16-bit at [Rn] to Rd

; load unsigned 16-bit at [Rn+off] to Rd

; load signed 16-bit at [Rn] to Rd

; load signed 16-bit at [Rn+off] to Rd

; load unsigned 8-bit at [Rn] to Rd

; load unsigned 8-bit at [Rn+off] to Rd

; load signed 8-bit at [Rn] to Rd

; load signed 8-bit at [Rn+off] to Rd

; store 32-bit Rt to [Rn]

; store 32-bit Rt to [Rn+off]

; store least sig. 16-bit Rt to [Rn]

; store least sig. 16-bit Rt to [Rn+off]

; store least sig. 8-bit Rt to [Rn]

; store least sig. 8-bit Rt to [Rn+off]

; push 32-bit Rt onto stack

; pop 32-bit number from stack into Rd

; set Rd equal to the address at label

; set Rd equal to op2

; set Rd equal to im16, im16 is 0 to 65535

; set Rd equal to -op2

Interrupt Instructions

CPSIE  I
CPSID  I 

; enable interrupts  (I=0)

 ; disable interrupts (I=1)

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